System-on-chip (SoC) integration requires formation of many different types of semiconductor devices on the same chip to enable various features offered by the integrated semiconductor devices. Many such SoC semiconductor chips employ semiconductor devices for power applications that are subjected to high voltages as well as high performance semiconductor devices that employ typical low supply voltages. For example, a high voltage power amplifier/switch may be employed in an SoC semiconductor chip to provide a high voltage output. Likewise, a high voltage rectifier in an SoC semiconductor chip may enable a low voltage power supply network from a high voltage power supply connected to the SoC semiconductor chip.
On one hand, to enable power semiconductor devices employing a field effect transistor, a thick gate dielectric is required. Power semiconductor devices in an SoC semiconductor chip are subjected to a high voltage, which may be in the range from about 40 V to about 120 V. To prevent dielectric breakdown, the thickness of the gate dielectric for the field effect transistor needs to be thick enough so that the electric field within the gate dielectric is less than a dielectric breakdown field strength within the gate dielectric.
On the other hand, thin gate dielectrics are preferred to enable high performance semiconductor devices on a semiconductor substrate. Particularly, the thickness of gate dielectrics comprising a silicon oxide based dielectric material is limited on a semiconductor-on-insulator (SOI) substrate since the thickness of a top semiconductor layer is finite. In many cases, the thickness of the top semiconductor layer is less than 100 nm, and even less than 50 nm to enable high performance semiconductor devices. In this case, formation of a thick silicon oxide based gate dielectric may consume the entire thickness of the top semiconductor layer, or render the remaining portion of the top semiconductor layer too thin to form a functional power semiconductor device. Formation of a high dielectric constant (high-k) gate dielectric at a sufficiently great thickness to enable a power semiconductor device is difficult, and may take excessive processing time and cost since formation of high-k gate dielectric typically employs atomic layer deposition (ALD), which has a low deposition rate.
Thus, the requirement for high performance field effect transistors and the requirement for high voltage field effect transistors for power applications are contradictory on an SOI substrate, rendering formation of an SoC semiconductor chip providing both high performance field effect transistors and high voltage field effect transistors difficult.
In view of the above, there exists a need for a semiconductor structure including a high performance field effect transistor and a high voltage field effect transistor on a semiconductor-on-insulator (SOI) substrate that does not compromise the performance of the high performance field effect transistor by limiting the thickness of a top semiconductor layer or compromise the performance of the high voltage field effect transistor by limiting the thickness of a gate dielectric employed in the high voltage field effect transistor.
Further, there exists a need for a design structure for such a semiconductor structure.